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What will computer chips look like in 2045?

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Original episode audio — courtesy of Dwarkesh Podcast

The episode examines a central tension in the future of computing: how much chip technology can advance when AI demand is growing faster than manufacturing capacity can readily expand. Host Dwarkesh Patel spent two days touring Intel’s most advanced fab and speaking with its technical leadership; the show notes do not name individual guests. Rather than offering a definitive picture of chips in 2045, the episode explores the transistor, wiring, packaging and production changes that could shape them.

The technical discussion spans gate-all-around transistors, backside power, stacked transistors known as CFET, and hybrid bonding, supported by animated explainers. It also examines bringing up a new process node, lessons from Intel’s 10nm experience, replacing copper wires with ruthenium, and the chip-to-chip bottleneck. Together, these topics frame progress as a problem extending beyond individual transistors to connections within and between chips, as well as the manufacturing processes needed to deliver those changes.

The immediate context is the scale of AI’s demand for compute. The notes state that AI compute has grown threefold annually over the last decade, while attributing to Intel’s CTO the assessment that today’s global stock of chipmaking tools would allow Intel to only double leading-edge wafer production. Those figures concern different measures—compute growth and wafer-production capacity—but they motivate the episode’s question about how foundries can delay demand substantially outstripping supply. The discussion also raises company-specific trade-offs, including why High-NA EUV pays off for Intel but not TSMC, and why stacked transistors take a decade to ship; the notes do not provide the detailed arguments behind either topic.

Several questions remain open in the supplied material: which technical changes can most effectively ease supply constraints, whether Intel can catch up to TSMC, and how fundamentally fabs could be redesigned. The closing discussion covers Terafab and rethinking the fab from scratch. The notes establish these as subjects of inquiry, not settled conclusions, and provide no firm deployment roadmap through 2045.

Why it matters

For executives planning AI-dependent products or infrastructure, semiconductor availability deserves attention alongside model capabilities and software progress. Capacity assumptions should distinguish compute demand from wafer output rather than treating the episode’s growth figures as directly comparable forecasts. Procurement and investment planning should also account for long technology-development cycles and differences between foundries’ manufacturing choices. The practical implication is to test plans against constrained hardware supply rather than assume demand will automatically induce rapid production expansion.

Key takeaways

  • Patel’s reporting draws on two days at Intel’s most advanced fab and conversations with its technical leadership.
  • The notes state that AI compute has grown 3x annually for the last decade; this is a historical claim, not a forecast through 2045.
  • Intel’s CTO is cited as saying that today’s global chipmaking-tool stock would allow Intel to only double leading-edge wafer production.
  • The technical agenda includes gate-all-around transistors, backside power, CFET and hybrid bonding, with animated explainers to make the concepts accessible.
  • Manufacturing topics include new process-node bring-up, lessons from Intel’s 10nm experience and replacing copper wires with ruthenium.
  • The episode examines why stacked transistors take a decade to ship and why chip-to-chip connections can become a bottleneck.
  • High-NA EUV’s differing economics for Intel and TSMC, Intel’s ability to catch up to TSMC, and redesigning fabs are discussion topics whose conclusions are not supplied in the notes.

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Books, articles & resources mentioned

Spotted in this episode — worth a look if you want to go further.

  • Resource

    animated explainers

    Dwarkesh Podcast

    Created for the episode to explain difficult concepts in future chip technology.

  • Resource

    flashcards

    Dwarkesh Patel

    Patel shared flashcards covering concepts he learned while preparing for the episode.

  • Tool

    YouTube

    The notes direct readers to watch the episode on YouTube.

  • Resource

    transcript

    The notes offer a transcript as an alternative way to access the episode.

  • Tool

    WorkOS

    WorkOS

    A sponsor offering enterprise features including SSO, SCIM, RBAC, audit logs and authentication for agents.

  • Tool

    magic-trace

    Jane Street

    A sponsor segment describes this tool for analyzing and debugging trading systems as built on Intel’s Processor Trace feature.

  • Tool

    Processor Trace

    Intel

    This Intel chip feature is identified as the foundation for Jane Street’s magic-trace tool.

  • Tool

    Antithesis’ testing platform

    Antithesis

    A sponsor segment describes deterministic testing that reproduces bugs by controlling sources of nondeterminism in Intel’s x86 architecture.

  • Resource

    Terafab

    The closing segment mentions Terafab alongside rethinking the fab from scratch, without further description in the notes.

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Independent summary by PodPulse Digest based on the episode's public show notes. Not affiliated with Dwarkesh Podcast. All rights to the original audio belong to its creators.

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